Measured Latency Introduced by RF Network-on-Chip (RFNoC) Architecture

Abstract

Radio Frequency Network-on-Chip (RFNoC) is a recently developed architecture for Universal Software Radio Peripheral (USRP) Software-Defined Radios (SDR). This new architecture works to leverage the USRP's field-programmable gate array (FPGA) chip to configure digital signal processing (DSP) blocks. A USRP-based SDR application benefits from high adaptability and quicker development time but typically shows high latency. The research in this paper focuses on measuring the latency introduced by the RFNoC architecture in a consistent and repeatable manner to provide a benchmark for SDR applications. By focusing on the \textit{tvalid} interface of the AXI data stream and probing it at different points within the layers of RFNoC architecture, data packets can be tracked and the latency can be quantified and characterized. This study seeks to provide a better understanding of RFNoC's capabilities so that users can determine whether it meets their performance needs and to recommend future improvements by diagnosing the layers of RFNoC where the most latency is incurred.