Designing a RFNoC Block implementing a SISO Processor using High-Level Synthesis

Authors

  • Andrea Guerrieri EPFL-LAP

Keywords:

RFNoC, SISO, FEC, High-Level Synthesis, DSP, FPGA, SDR

Abstract

RFNoC(RF Network on Chip) is an open-source processing tool developed by Ettus Research. SISO Processor(Soft In Soft Out) is one of the basic component used in modern FEC(Forward Error Correcting) techniques such as Turbo Codes and LDPC. This paper would to presents an in-progress RFNoC block development which implement a SISO Processor as answer to "The RFNoC & Vivado HLS Challenge" sponsored by Ettus Research and Xilinx.

References

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Published

2017-09-05

Issue

Vol. 2 No. 1 (2017): Proceedings of the 7th GNU Radio Conference

Section

Articles

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