Channelization using RFNoC
Abstract
This document will review the derivation of the M/2 channelizer structure found in (Harris F., 2010). The document will then provide the detailed FPGA implementation of the architecture. The FPGA implementation is specific to the Xilinx architecture since it utilizes the pipelining functionality of the DSP48 cores found in 7 series devices. The implementation is fully pipelined to achieve maximum FMax performance and achieves maximum throughput.
Published
2017-09-05
How to Cite
VALLANCE, Phillip.
Channelization using RFNoC.
Proceedings of the GNU Radio Conference, [S.l.], v. 2, n. 1, p. 7, sep. 2017.
Available at: <https://pubs.gnuradio.org/index.php/grcon/article/view/18>. Date accessed: 24 dec. 2024.
Section
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