Channelization using RFNoC
This document will review the derivation of the M/2 channelizer structure found in (Harris F., 2010). The document will then provide the detailed FPGA implementation of the architecture. The FPGA implementation is specific to the Xilinx architecture since it utilizes the pipelining functionality of the DSP48 cores found in 7 series devices. The implementation is fully pipelined to achieve maximum FMax performance and achieves maximum throughput.
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