Channelization using RFNoC

Authors

  • Phillip Vallance Vallance Engineering LLC

Keywords:

software radio; gnu radio; DSP; channelizer; GRCON

Abstract

This document will review the derivation of the M/2 channelizer structure found in (Harris F., 2010). The document will then provide the detailed FPGA implementation of the architecture. The FPGA implementation is specific to the Xilinx architecture since it utilizes the pipelining functionality of the DSP48 cores found in 7 series devices. The implementation is fully pipelined to achieve maximum FMax performance and achieves maximum throughput.

References

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Published

2017-09-05

Issue

Vol. 2 No. 1 (2017): Proceedings of the 7th GNU Radio Conference

Section

Articles

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