FPGA Partial Reconfiguration in Software Defined Radio Devices
Many SDR systems make effective use of FPGAs for data acquisition and heavy lifting DSP processing. This has resulted in several dedicated frameworks being developed, RFNoC being the most renowned. Even though FPGAs fabrics are, by their nature, reconfigurable, SDR systems often fail in exploiting this interesting opportunity at run-time. In this paper, we show how it is possible to make effective use of the Partial Reconfiguration capabilities of modern FPGA devices, extending the range of applications RFNoC can be applied to. In particular, it allows the live reconfiguration of signal processing chains, for instance to switch between wireless standards. This results in a better use of the limited FPGA resources by time-sharing them between processing blocks. Unfortunately, support for Partial Reconfiguration is not yet available in the software stack of commercially-available SDR devices. Our work thus aims at encouraging its integration.
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